Rectification method for lookup-table type FPGA's
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Incremental logic synthesis through gate logic structure identification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Design and design automation of rectification logic for engineering change
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Automating Logic Rectification by Approximate SPFDs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Logic synthesis for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AutoFix: a hybrid tool for automatic logic rectification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic design verification via test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixing Design Errors With Counterexamples and Resynthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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For a design with multiple functional errors, multiple patches are usually needed to correct the design. Previous works on logic rectification are limited to either single-fix or partial-fix rectifications. In other words, only one or part of the erroneous behaviors can be fixed in one iteration. As a result, it may lead to unnecessarily large patches or even failure in rectification. In this paper, we propose a multi-patch generation technique by interpolation with cofactor reduction. In particular, our method considers multiple errors in the design simultaneously and generates multiple patches to fix these errors. Experimental results show that the proposed method is effective on a set of large circuits, including the circuits synthesized from industrial register-transfer level (RTL) designs.