Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
Match and replace: a functional ECO engine for multi-error circuit rectification
Proceedings of the International Conference on Computer-Aided Design
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Microprocessors & Microsystems
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In this paper, we propose a resynthesis framework, called COunterexample-guided REsynthesis (CoRe), that automatically corrects errors in digital designs. The framework is based on a simulation-based abstraction technique and performs an error correction through two innovative circuit resynthesis solutions: distinguishing-power search and goal-directed search, which modify the functionality of circuits' internal nodes to match the correct behavior. In addition, we propose a compact encoding of resynthesis information, called the Pairs of Bits to be Distinguished, which is a key enabler for our resynthesis techniques. Compared with previous solutions, CoRe is more powerful for the following reasons: (1) It can fix a broader range of error types because it is not bounded by specific error models; (2) it derives the correct functionality from simulation vectors without requiring golden netlists; and (3) it can be applied with a broad range of verification flows, including formal and simulation-based flows.