Proceedings of the 39th annual Design Automation Conference
Engineering change using spare cells with constant insertion
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SafeResynth: A new technique for physical synthesis
Integration, the VLSI Journal
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Spare cells with constant insertion for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Sequential logic rectifications with approximate SPFDs
Proceedings of the Conference on Design, Automation and Test in Europe
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
Match and replace: a functional ECO engine for multi-error circuit rectification
Proceedings of the International Conference on Computer-Aided Design
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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During the process of very large scale integration design, specifications are often changed. To preserve as large a portion of the engineering effort as possible, it is desirable that such changes will not lead to a very different design. In this work, we consider logic synthesis algorithms for handling engineering changes. To solve it, we propose a combination of multiple-error diagnosis and logic minimization techniques. Given a new specification and an existing synthesized network, our algorithms first identify the candidate signals in the network, and then synthesize the candidate functions. The synthesis step utilizes the existing network as much as possible so that the new specification can be realized with minimal changes