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In this paper, we present techniques for partial synthesis through sampling mostly for combinational circuits. Here partial synthesis means that most parts of the target circuits are fixed whereas the missing portions must be logic synthesized from scratch. By modeling the missing portions with Look Up Table (LUT) or uninterpreted function (UF), their synthesis and verification problems can be formulated as Quantified Boolean Formulae (QBF). We solve these QBF by repeatedly applying a two step procedure i.e., synthesizing circuits from sample simulation results (necessary conditions) followed by formal verification on the synthesized ones with their specifications for the entire circuits (sufficient conditions). If a circuit is not correct, a counter example is automatically generated which is added to the sampling in the next iteration. With state-of-the-art combinational formal equivalence checkers, our experiments show that large circuits having more than hundreds of thousands of gates can be successfully processed with small numbers of repetitions (in the order of hundreds). Next, we extend the techniques in such a way that no formal specifications nor formal verifiers are available, but only simulation models are used for "correct" partial synthesis. This is achieved by searching for multiple different solution circuits for missing portions which behave the same for the sampled inputs but differently with another input. By repeating this process, we can narrow down the search space, and the solution circuit may become only one which should be the "correct" partial synthesis. We show successfully experimental results with small numbers of repetitions for circuits where 32-inputs/32-outputs sub-circuits are missing.