The turn model for adaptive routing
Journal of the ACM (JACM)
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Wormhole routing techniques for directly connected multicomputer systems
ACM Computing Surveys (CSUR)
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Introducing Core-Based System Design
IEEE Design & Test
Automating the Design of SOCs Using Cores
IEEE Design & Test
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Scalable Communication-Centric SoC Interconnect Architecture
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Packetized On-Chip Interconnect Communication Analysis for MPSoC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Micro-Network for SoC: Implementation of a 32-Port SPIN network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Co-synthesis of a configurable SoC platform based on a network on chip architecture
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Application driven traffic modeling for NoCs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Area and performance optimization of a generic network-on-chip architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
The Power of Priority: NoC Based Distributed Cache Coherency
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Access Regulation to Hot-Modules in Wormhole NoCs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NoC-Based FPGA: Architecture and Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Layered switching for networks on chip
Proceedings of the 44th annual Design Automation Conference
Buffer sizing for QoS flows in wormhole packet switching NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
Fitting the router characteristics in NoCs to meet QoS requirements
Proceedings of the 20th annual conference on Integrated circuits and systems design
Router architecture for high-performance NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
Simulink based hardware-software codesign flow for heterogeneous MPSoC
Proceedings of the 2007 Summer Computer Simulation Conference
A simplified executable model to evaluate latency and throughput of networks-on-chip
Proceedings of the 21st annual symposium on Integrated circuits and system design
Executable formal specification and validation of NoC communication infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
MOTIM: an industrial application using nocs
Proceedings of the 21st annual symposium on Integrated circuits and system design
A Hardware-Software Design Framework for Distributed Cellular Computing
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
Microprocessors & Microsystems
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
A generic implementation model for the formal verification of networks-on-chips
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Design Trade-offs in Customized On-chip Crossbar Schedulers
Journal of Signal Processing Systems
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs
SOC'09 Proceedings of the 11th international conference on System-on-chip
On a web-graph-based micronetwork architecture for SoCs
International Journal of Computers and Applications
Partially reconfigurable point-to-point interconnects in Virtex-II pro FPGAs
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Systematic customization of on-chip crossbar interconnects
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
Reconfigurable Networks on Chip: DRNoC architecture
Journal of Systems Architecture: the EUROMICRO Journal
Evaluating the impact of task migration in multi-processor systems-on-chip
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Flexible interconnection network for dynamically and partially reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of low-overhead configurable source routing tables for network interfaces
Proceedings of the Conference on Design, Automation and Test in Europe
A monitor interconnect and support subsystem for multicore processors
Proceedings of the Conference on Design, Automation and Test in Europe
A parallel genetic algorithm on a multi-processor system-on-chip
IEA/AIE'10 Proceedings of the 23rd international conference on Industrial engineering and other applications of applied intelligent systems - Volume Part II
CAFES: A framework for intrachip application modeling and communication architecture design
Journal of Parallel and Distributed Computing
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach
Proceedings of the 4th International Workshop on Network on Chip Architectures
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
Clustered NOC, a suitable design for group communications in Network on Chip
Computers and Electrical Engineering
Benchmarking mesh and hierarchical bus networks in system-on-chip context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Hunting deadlocks efficiently in microarchitectural models of communication fabrics
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Static routing for applications mapped on NoC platform using ant colony algorithms
International Journal of High Performance Systems Architecture
ACO-Based static routing for network-on-chips
ICCSA'12 Proceedings of the 12th international conference on Computational Science and Its Applications - Volume Part I
Optimizing heterogeneous NoC design
Proceedings of the International Workshop on System Level Interconnect Prediction
Efficient execution of networked MPSoC models by exploiting multiple platform levels
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Reconfigure router design and evaluation for the FPGA-friendly SoCWire network-on-chip
Proceedings of the Annual FPGA Conference
Routing for applications in NoC using ACO-based algorithms
Applied Soft Computing
Hybrid interconnect design for heterogeneous hardware accelerators
Proceedings of the Conference on Design, Automation and Test in Europe
Expert Systems with Applications: An International Journal
FlexTiles: a globally homogeneous but locally heterogeneous manycore architecture
Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms
On the design space exploration through the Hellfire Framework
Journal of Systems Architecture: the EUROMICRO Journal
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The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional on-chip bus architectures. This paper reviews the state of the art in networks on chip. Then, it describes an infrastructure called Hermes, targeted to implement packet-switching mesh and related interconnection architectures and topologies. The basic element of Hermes is a switch with five bi-directional ports, connecting to four other switches and to a local IP core. The switch employs an XY routing algorithm, and uses input queuing. The main design objective was to develop a small size switch, enabling its immediate practical use. The paper also presents the design validation of the Hermes switch and of a network on chip based on it. A Hermes NoC case study has been successfully prototyped in hardware as described in the paper, demonstrating the functionality of the approach. Quantitative data for the Hermes infrastructure is advanced.