The turn model for adaptive routing
Journal of the ACM (JACM)
A universal proof technique for deadlock-free routing in interconnection networks
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
A General Theory for Deadlock Avoidance in Wormhole-Routed Networks
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
OCCN: A Network-On-Chip Modeling and Simulation Framework
Proceedings of the conference on Design, automation and test in Europe - Volume 3
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A tool for automatic detection of deadlock in wormhole networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks
PDP '10 Proceedings of the 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing
A Fast and Verified Algorithm for Proving Store-and-Forward Networks Deadlock-Free
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
IEEE Transactions on Parallel and Distributed Systems
On Necessary and Sufficient Conditions for Deadlock-Free Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
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Wormhole switching is a switching technique nowadays commonly used in networks-on-chips (NoCs). It is efficient but prone to deadlock. The design of a deadlock-free adaptive routing function constitutes an important challenge. We present a novel algorithm for the automatic verification that a routing function is deadlock-free in wormhole networks. A sufficient condition for deadlock-free routing and an associated algorithm are defined. The algorithm is proven complete for the condition. The condition, the algorithm, and the correctness theorem have been formalized and checked in the logic of the ACL2 interactive theorem proving system. The algorithm has a time complexity in O(N3), where N denotes the number of nodes in the network. This outperforms the previous solution of Taktak et al. by one degree. Experimental results confirm the high efficiency of our algorithm. This paper presents a formally proven correct algorithm that detects deadlocks in a 2D-mesh with about 4000 nodes and 15000 channels within seconds.