Reconfigure router design and evaluation for the FPGA-friendly SoCWire network-on-chip

Authors:
Arash Farhadi Beldachi;Jose L. Nunez-Yanez
Affiliations:
University of Bristol, Bristol, UK;University of Bristol, Bristol, UK
Venue:
Proceedings of the Annual FPGA Conference
Year:
2012

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Abstract

This paper extends the System-on-Chip Wire (SoCWire) Network-On-Chip (NoC) with a reconfigurable router suitable for building FPGA-based NoC. Different configurations of the SoCWireRouter with a varying number of local and multi-dimensional ports have been used to create a number of equivalent networks. The system is prototyped in a FPGA-based PCIexpress board with the NoC connected to a softcore processor that acts as system master and monitor. The evaluation of equivalent networks for a fixed number of computing nodes under a synthetic and realistic traffic loads indicates the ideal SoCWireRouter topology depends on the design objectives and expected traffic pattern.