A networks-on-chip emulation/verification framework
International Journal of High Performance Systems Architecture
Reconfigure router design and evaluation for the FPGA-friendly SoCWire network-on-chip
Proceedings of the Annual FPGA Conference
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The emulation and functional validation are essential to assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection networks architecture. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy, and decrease usage of the resource of field programmable gate array.