A simplified executable model to evaluate latency and throughput of networks-on-chip

Authors:
Luciano Ost;Fernando G. Moraes;Leandro Möller;Leandro Soares Indrusiak;Manfred Glesner;Sanna Määttä;Jari Nurmi
Affiliations:
PUCRS-FACIN, Porto Alegre, Brazil;PUCRS-FACIN, Porto Alegre, Brazil;TECHNISCHE UNIVERSITÄT DARMSTADT, DARMSTADT, Germany;TECHNISCHE UNIVERSITÄT DARMSTADT, DARMSTADT, Germany;TECHNISCHE UNIVERSITÄT DARMSTADT, DARMSTADT, Germany;TAMPERE UNIVERSITY OF TECHNOLOGY, TAMPERE, Finland;TAMPERE UNIVERSITY OF TECHNOLOGY, TAMPERE, Finland
Venue:
Proceedings of the 21st annual symposium on Integrated circuits and system design
Year:
2008

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Abstract

This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.