On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 41st annual Design Automation Conference
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simplified executable model to evaluate latency and throughput of networks-on-chip
Proceedings of the 21st annual symposium on Integrated circuits and system design
Flexible and abstract communication and interconnect modeling for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A flexible framework for communication evaluation in SoC design
International Journal of Parallel Programming
Evaluating SoC Network Performance in MPEG-4 Encoder
Journal of Signal Processing Systems
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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One of the key elements in Multi-Processor Systems-on-Chip (MPSoC) design is to select the optimal on-chip interconnect architecture, in order to maximize the overall system performance.This paper proposes a flexible MPSoC platform, designed for a target application, which allows customizing the interconnect by selecting various architectures. It allows fast building of executable models from architecture specifications and performance evaluation using the cycle-accurate cosimulation.We experimented a DivX encoder application with three different interconnects: DMS (Distributed Memory Server), AMBA bus and Octagon Network-on-Chip (NoC). The simulation results relative to performance metrics such as, average latency, throughput and execution time allowed to compare these different interconnect architectures, to verify the application real-time constraints and to propose further optimizations.