A flexible framework for communication evaluation in SoC design

Authors:
Praveen Kalla;X. Sharon Hu;Jörg Henkel
Affiliations:
Broadcom, Matawan, NJ;Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN;Department of Computer Science, University of Karlsruhe, Karlsruhe, Germany
Venue:
International Journal of Parallel Programming
Year:
2008

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Abstract

Multi-core System-on-Chips (SoCs) with on-chip networks are becoming a reality after almost a decade of research. One challenge in developing such SoCs is the need of efficient and accurate simulators for design space exploration. This paper addresses this need by presenting SoCExplore, a framework for last communication-centric design space exploration of complex SoCs with network-based interconnects. Efficiency is achieved through abstraction of computation as a high-level trace, while accuracy is maintained through cycle-accurate interconnect simulation. The flexibility offered allows for fast partition/mapping and interconnect design space exploration. In a case study, a speed-up of 94% over architectural simulation is obtained for the MPEG application. A critical evaluation of the capabilities of our (or any trace based) framework is also provided.