Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Throughput-centric routing algorithm design
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
FPGA-Based System Design
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Worst-case Traffic for Oblivious Routing Functions
IEEE Computer Architecture Letters
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Statistical Approach to NoC Design
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
Static virtual channel allocation in oblivious routing
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
An insertion loss balance aware routing scheme in photonic network on chip
ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
A minimalist cache coherent MPSoC designed for FPGAs
International Journal of High Performance Systems Architecture
Capacity optimized NoC for multi-mode SoC
Proceedings of the 48th Design Automation Conference
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
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We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instances with good performance and low cost. Our architecture minimizes the cost of supporting a wide range of design instances with given throughput requirements by balancing the amount of efficient hard-coded NoC infrastructure and the allocation of"soft" networking resources at configuration time. Although traffic patterns are design-specific, the physical link infrastructure is a performance bottleneck, and hence should be hard-coded. It is therefore important to employ routing schemes that allow for high flexibility to efficiently accommodate different traffic patterns during configuration. We examine the required capacity allocation for supporting a collection of typical traffic patterns on such chips under a number of routing schemes. We propose a new routing scheme, Weighted Ordered Toggle (WOT), and show that it allows high design flexibility with low infrastructure cost. Moreover, WOT utilizes simple, small-area, on-chip routers, and has low memory demands.