A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Traffic generation and performance evaluation for mesh-based NoCs
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Application driven traffic modeling for NoCs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Networks on chip (NoCs) are communication infrastructures that offer parallelism and scalability. Most NoC designs employ wormhole packet switching, since this switching mode optimizes the use of NoC resources. However, this mode may introduce jitter, possibly producing packet loss, due to the violation of temporal QoS constraints. One technique to deal with jitter is to introduce a decoupling buffer (D-buffer) on the target IP. This buffer receives data from the NoC with jitter, while the target IP consumes data from this buffer at the application rate, without jitter. Two problems must be solved to implement D-buffers: (i) which size must the buffer have? (ii) how much buffer space should be filled before data consumption starts (threshold)? This work proposes a general method to define D-buffer size and threshold, considering the influence of packaging, arbitration, routing and concurrency between flows. Before presenting the method, the paper extends a previous traffic model for stream applications and characterizes jitter sources in wormhole packet switching. The experimental results obtained with the proposed method showed that simple traffic models employing constant frame sizes result in small D-buffers. On the other hand, employing video frames from application traces (i.e. real application data) increases buffer size and threshold, still suppressing jitter. Application traces highlight the threshold parameter importance.