Hunting deadlocks efficiently in microarchitectural models of communication fabrics

Authors:
Freek Verbeek;Julien Schmaltz
Affiliations:
Radboud University Nijmegen, The Netherlands;Open University of the Netherlands, The Netherlands
Venue:
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Year:
2011

Citing 8
Cited 2

Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
A Survey of Wormhole Routing Techniques in Direct Networks

Computer
Networks on Chips: A New SoC Paradigm

Computer
An Interconnect Architecture for Networking Systems on Chips

IEEE Micro
HERMES: an infrastructure for low area overhead packet-switching networks on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC

Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Verifying deadlock-freedom of communication fabrics

VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics

CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification

Towards the formal verification of cache coherency at the architectural level

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Communication fabries constitute an important challenge for the design and verification of multi-core architectures. To enable their formal analysis, microarchitectural models have been proposed as an efficient abstraction capturing the high-level structure of designs. We propose a novel algorithm to deadlock verification of microarchitectural designs. The basic idea of our algorithm is to capture the structure of the wait-for relations of a microarchitectural model in a labelled waitin-graph and to express a deadlock as a feasible closed subgraph of the waiting-graph. We apply our algorithm to academic and industrial Networks-on-Chip (NoC) designs. With examples we show that our tool is fast, scalable, and capable of detecting intricate message-dependent deadlocks. Deadlocks in networks with thousands of components are detected within a few seconds.