Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Lamport clocks: verifying a directory cache-coherence protocol
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Parameterized Verification of a Cache Coherence Protocol: Safety and Liveness
VMCAI '02 Revised Papers from the Third International Workshop on Verification, Model Checking, and Abstract Interpretation
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
An ACL2 Proof of Write Invalidate Cache Coherence
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic Verification of Parameterized Cache Coherence Protocols
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Constraint-Based Verification of Parameterized Cache Coherence Protocols
Formal Methods in System Design
Formal Verification and its Impact on the Snooping versus Directory Protocol Debate
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Combining Theorem Proving with Model Checking through Predicate Abstraction
IEEE Design & Test
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Rapid parameterized model checking of snoopy cache coherence protocols
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols
Formal Methods in System Design
Fractal Coherence: Scalably Verifiable Cache Coherence
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Verifying deadlock-freedom of communication fabrics
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Counterexample guided invariant discovery for parameterized cache coherence verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Hunting deadlocks efficiently in microarchitectural models of communication fabrics
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model-checking, have been successful at verifying high-level protocols, but, to the best of our knowledge, the verification of cache coherency at the architectural level is still an open issue. All existing verification efforts assume a reliable interconnect, that is, messages eventually reach their destination. We discuss the challenge of discharging this assumption at the architectural level where implementation details of the interconnect are mixed with a cache coherency protocol. Our automatic approach is based on a well-defined set of primitives to express architectural models, a generic model of communication fabrics expressed in an automated theorem proving system, and a dedicated algorithm for deadlock and livelock detection. We argue that reliability depends on the interaction between the interconnect and the cache coherency protocol. They must be verified altogether as their combination creates intricate message dependencies. We sketch our verification approach and apply it to a simple write-invalidate protocol on the Spidergon network-on-chip from STMicroelectronics. Our approach is promising. For this simple protocol, networks with tens of agents and hundreds of components can be analyzed within seconds.