Parallel program design: a foundation
Parallel program design: a foundation
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
System design methodology of ultraSPARC-I
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
CACHET: an adaptive cache coherence protocol for distributed shared-memory systems
ICS '99 Proceedings of the 13th international conference on Supercomputing
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Model checking
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Architecture and design of AlphaServer GS320
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Directed explicit model checking with HSF-SPIN
SPIN '01 Proceedings of the 8th international SPIN workshop on Model checking of software
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Formal Design of Cache Memory Protocols in IBM
Formal Methods in System Design
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Verifying Systems with Replicated Components in Murphi
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Reducing Model Checking of the Many to the Few
CADE-17 Proceedings of the 17th International Conference on Automated Deduction
A consistent and complete deductive system for the verification of parallel programs
STOC '76 Proceedings of the eighth annual ACM symposium on Theory of computing
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Improving Multiple-CMP Systems Using Token Coherence
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
Proceedings of the 2007 ACM symposium on Applied computing
Cache coherence techniques for multicore processors
Cache coherence techniques for multicore processors
Going with the flow: parameterized verification using message flows
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Automatic non-interference lemmas for parameterized model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Hierarchical cache coherence protocol verification one level at a time through assume guarantee
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Towards the formal verification of cache coherency at the architectural level
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
The Journal of Supercomputing
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Multicore architectures are considered inevitable, given that sequential processing hardware has hit various limits. Unfortunately, the memory system of multicore processors is a huge bottleneck. To combat this problem, one needs to design aggressively optimized cache coherence protocols. This introduces the design correctness problem for advanced cache coherence protocols which will be hierarchically organized for scalable designs. Experiences show that monolithic formal verification will not scale to hierarchical designs. Hence, one needs to handle the complexity of several coherence protocols running concurrently, i.e. hierarchical protocols, using compositional techniques.To solve the problem, we develop a family of compositional approaches all based on assume-guarantee reasoning to reducing the verification complexity. We show that for the three hierarchical protocols with certain realistic features that we developed for multiple chip-multiprocessors, more than a 20-fold improvement in terms of the number of states visited can be achieved. Also, to avoid false alarms wasting designer time, we have developed an error trace justification method to eliminate false alarms using heuristics that also capitalize on our assume-guarantee approaches. Our techniques need no special tool support. They can be carried out using the widely used Murphi model checker along with support tools for abstraction and error trace justification that we have built.