A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Networks on chip
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
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The Network-on-Chip (NoC) concept has been identified as an attractive solution to the ever-increasing interconnect problem in complex System-on-Chip (SoC) designs. In this paper, we propose a highly scalable topology structure for NoC designs based on the web graph. This topology, named as Spidernet, is compared favourably to other five popular NoC topologies, including mesh, torus, fat tree, octagon, and spidergon in terms of node degree, network diameter, connection degree, average most short-circuit path, and average shortest wire length. We further propose a 2D layout design for Spidernet, and experiment results have confirmed its superiority over layouts derived from the above five competing topologies.