Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures

Authors:
Márcio Kreutz;César A. Marcon;Luigi Carro;Flávio Wagner;Altamiro A. Susin
Affiliations:
Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, RS, Brazil
Venue:
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Year:
2005

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Abstract

Networks-on-chip (NoCs) are communication architecture alternatives for complex Systems-on-Chip (SoCs) designs, due to their high scalability and bandwidth. In this paper, we consider a heterogeneous NoC as an alternative to match performance and energy requirements for dedicated applications. By employing an optimized mix of different routers, a heterogeneous network optimized for latency and energy consumption is achieved. A dedicated data structure, the Application Communication Pattern (ACP), models the application, enabling the specification of the communication requirements among cores, together with their execution performance. ACP allows fast analysis, helping the system designer to evaluate the communication performance of a NoC-based system; this performance strongly depends on the placement of the cores, and it is computationally hard to find the optimal placement. An optimization algorithm mixes different router architectures - composing a heterogeneous NoC - and finds optimal placements for application cores. Therefore, a heterogeneous NoC can be achieved, which complies to the application requirements with minimum latency and energy, enabling one to obtain the Pareto curve relating latency and energy for a given application.