The Need for Reconfigurable Routers in Networks-on-Chip

Authors:
Debora Matos;Caroline Concatto;Luigi Carro;Fernanda Kastensmidt;Altamiro Susin
Affiliations:
Informatics Institute, Electrical Engineering Dept., Federal University of Rio Grande do Sul --- UFRGS, Porto, Brazil;Informatics Institute, Electrical Engineering Dept., Federal University of Rio Grande do Sul --- UFRGS, Porto, Brazil;Informatics Institute, Electrical Engineering Dept., Federal University of Rio Grande do Sul --- UFRGS, Porto, Brazil;Informatics Institute, Electrical Engineering Dept., Federal University of Rio Grande do Sul --- UFRGS, Porto, Brazil;Informatics Institute, Electrical Engineering Dept., Federal University of Rio Grande do Sul --- UFRGS, Porto, Brazil
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

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Abstract

There are many examples in the literature of applications that show different communication needs within a MPSoC. Very often cores interconnected through a Network-on-Chip have routers containing different buffers size, with different clock speed requirements. In this context, we are proposing a dynamic reconfigurable router for a NoC. With the proposed architecture it is possible to reconfigure the depth of each FIFO of the channel inside the routers. It allows more reusability in the NoC since the FIFO depth in the channels can be defined in accordance with the application. Besides, a buffer that is not used by its own channel can be used by others channel, reducing the power consumption.