Congestion-aware scheduling for NoC-based reconfigurable systems

Authors:
Hung-Lin Chao;Yean-Ru Chen;Sheng-Ya Tung;Pao-Ann Hsiung;Sao-Jie Chen
Affiliations:
National Chung Cheng University, Taiwan, R.O.C.;National Taiwan University, Taipei, Taiwan, R.O.C.;National Chung Cheng University, Taiwan, R.O.C.;National Chung Cheng University, Taiwan, R.O.C.;National Taiwan University, Taipei, Taiwan, R.O.C.
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 10
Cited 0

The turn model for adaptive routing

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
TGFF: task graphs for free

Proceedings of the 6th international workshop on Hardware/software codesign
Principles and Practices of Interconnection Networks

Principles and Practices of Interconnection Networks
Operating-system controlled network on chip

Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Key research problems in NoC design: a holistic perspective

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Time and energy efficient mapping of embedded applications onto NoCs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse

Proceedings of the 19th ACM Great Lakes symposium on VLSI
Traffic Aware Scheduling Algorithm for Network on Chip

ITNG '09 Proceedings of the 2009 Sixth International Conference on Information Technology: New Generations

Quantified Score

Hi-index	0.00

Visualization

Abstract

Network-on-Chip (NoC) is becoming a promising communication architecture in place of dedicated interconnections and shared buses for embedded systems. Nevertheless, it has also created new design issue such as communication congestion and power consumption. A major factor leading to communication congestion is mapping of application tasks to NoC. Latency, throughput, and overall execution time are all affected by task mapping. As a solution, an efficient run-time Congestion-Aware Scheduling (CWS) is proposed for NoC-based reconfigurable systems, which predicts traffic pattern based on the link utilization. The proposed algorithm alleviates the overall congestion, instead of only improving the current packet blocking situation. Our experiment results have demonstrated that compared to other existing congestion-aware algorithm, the proposed CWS algorithm can reduce the average communication latency by 66%, increase the average throughput by 32%, reduce the energy consumption by 23%, and decrease the overall execution by 32%.