Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms

Authors:
Sohaib Majzoub;Resve Saleh;Steven J. E. Wilton;Rabab Ward
Affiliations:
Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada;Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada;Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada;Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada
Venue:
SOC'09 Proceedings of the 11th international conference on System-on-chip
Year:
2009

Citing 12
Cited 1

Dynamic Power Management by Combination of Dual Static Supply Voltages

ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Impact of process variations on multicore performance symmetry

Proceedings of the conference on Design, automation and test in Europe
Temperature aware task scheduling in MPSoCs

Proceedings of the conference on Design, automation and test in Europe
Energy-aware synthesis of networks-on-chip implemented with voltage islands

Proceedings of the 44th annual Design Automation Conference
Thousand core chips: a technology perspective

Proceedings of the 44th annual Design Automation Conference
Variation-aware task allocation and scheduling for MPSoC

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Characterizing chip-multiprocessor variability-tolerance

Proceedings of the 45th annual Design Automation Conference
Many-core design from a thermal perspective

Proceedings of the 45th annual Design Automation Conference
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm

DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
PVT variation impact on voltage island formation in MPSoC design

ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Hotspot: acompact thermal modeling methodology for early-stage VLSI design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Energy optimization for many-core platforms: communication and PVT aware voltage-Island formation and voltage selection algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propse a novel approach to voltage island formation and core placement for energy optimization in manycore architectures under parameter variation at pre-fabrication stage. We group the cores into irregular "cloud-shaped" valtage islands. The island are created by balancing the desire to limit the spatial extent of each island, to reduce PVT impact, with the communication patterns between islands. Compared to using rectangular islands, our approach leads to power improvements between 10 and 12%.