ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Evaluation of voltage interpolation to address process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms
SOC'09 Proceedings of the 11th international conference on System-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Automating design of voltage interpolation to address process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Energy efficient computing is a first order design concern in portable devices. This paper describes a design approach that enables operation of a processor in various performance-energy modes. Depending on the workload and performance requirements, the processor can easily switch between these modes and save energy while still computing jobs in the required time. The proposed approach can also be used as an adaptive technique to compensate for process variation. We describe a feedback circuit to reduce power-performance spread due to process variation. We apply the adaptive technique to a 63-bit adder test circuit and show that the proposed method reduces the standard deviation of delay from 8.1% to 1.6%.