PVT variation impact on voltage island formation in MPSoC design

Authors:
Sohaib Majzoub;Resve Saleh;Rabab Ward
Affiliations:
SoC Research Lab, University of British Columbia, 2356 Main Mall Vancouver, Canada;SoC Research Lab, University of British Columbia, 2356 Main Mall Vancouver, Canada;Image Processing Lab, University of British Columbia, 2366 Main Mall Vancouver, Canada
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

Citing 0
Cited 2

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms

SOC'09 Proceedings of the 11th international conference on System-on-chip
Energy optimization for many-core platforms: communication and PVT aware voltage-Island formation and voltage selection algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

On-chip process, voltage, and temperature (PVT) variations are projected to be a major bottleneck in deep submicron design. Such variations can change performance characteristics and push power budgets beyond their limits. In a voltage/frequency island (VFI) design, the initial VFI's determined using optimization without considering PVT may not be suitable after fabrication. This can lead to degradation in energy that largely offsets the advantage of using VFI. Thus, it is crucial to include PVT variations in any prefabrication energy optimization algorithm to improve the post-fabricaiton design quality. In this paper, we present a methodology that can reduce the differences by including PVT variations in the optimization. We analyze the PVT impact for different PVT characteristics and propose ways to handle the issue with a penalty of only 3%.