Algorithms for facility location problems with outliers
SODA '01 Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Modeling repeaters explicitly within analytical placement
Proceedings of the 41st annual Design Automation Conference
Quadratic placement using an improved timing model
Proceedings of the 41st annual Design Automation Conference
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 ACM Symposium on Applied Computing
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
Power efficient voltage islanding for Systems-on-Chip from a floorplanning perspective
Proceedings of the Conference on Design, Automation and Test in Europe
Postplacement Voltage Island Generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Design for low power has become a key requirement in today's SoC design, especially for mobile applications. Multi-Vdd is an effective method to reduce both leakage and dynamic power. In a multi-Vdd design, cells of different supply voltages are often grouped into a small number of voltage islands, in order to avoid complex power supply system and excessive amount of level shifters. Recently, [9] proposed an elegant algorithm for voltage island grouping based on the physical proximity of the critical cells in a post-placement voltage assignment, and [10] proposed an efficient algorithm for voltage assignment which not only meets timing but also forms good proximity of the critical cells. However, due to insufficient slack, a few isolated critical cells (called outliers) may still exist in the resulting voltage assignment, causing disproportionately expensive penalty to the final voltage island grouping. In this paper, we propose a novel approach to improve the voltage assignment by automatic outlier detection followed by incremental placement. The outlier detection is based on a modified algorithm for the facility location problem. The incremental placement is guided by setting proper constraints on the paths containing the detected outliers, such that the outliers can be eliminated later. Our experiments on industry designs show that our algorithm leads to 12% -- 54% improvement in the final voltage island grouping, with quick turn around time.