A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reliability-Aware SOC Voltage Islands Partition and Floorplan
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Post-placement voltage island generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Voltage Island Generation under Performance Requirement for SoC Designs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
An enhanced congestion-driven floorplanner
WSEAS Transactions on Circuits and Systems
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
Proceedings of the 2009 international symposium on Physical design
Multi-voltage floorplan design with optimal voltage assignment
Proceedings of the 2009 international symposium on Physical design
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A revisit to voltage partitioning problem
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Circuits and Systems II: Express Briefs
Postplacement Voltage Island Generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The approximation scheme for peak power driven voltage partitioning
Proceedings of the International Conference on Computer-Aided Design
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI
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Energy efficiency has become one of the most important issues to be addressed in today's System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce the supply voltage. Multi-supply voltage (MSV) is thus introduced to provide higher flexibility in controlling the power and performance trade-off. In region-based MSV, circuits are partitioned into "voltage islands" where each island occupies a contiguous physical space and operates at one supply voltage. These tasks of island partitioning and voltage level assignments should be done simultaneously in the floorplanning process in order to take those important physical information into consideration. In this paper, we consider this core-based voltage island driven floorplanning problem including islands with power down mode, and propose a method to solve it. Given a candidate floorplan solution represented by a normalized Polish expression, we are able to obtain optimal voltage assignment and island partitioning (including islands with power down mode) simultaneously to minimize the total power consumption. Simulated annealing is used as the basic searching engine. By using this approach, we can achieve significant power savings (up to 50%) for all data sets, without any significant increase in area and wire length. Our floorplanner can also be extended to minimize the number of level shifters between different voltage islands and to simplify the power routing step by placing the islands in proximity to the corresponding power pins.