Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Approximation algorithms
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power distribution techniques for dual VDD circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A provably good approximation algorithm for power optimization using multiple supply voltages
Proceedings of the 44th annual Design Automation Conference
Voltage island-driven floorplanning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Proceedings of the 13th international symposium on Low power electronics and design
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of local interconnects on timing and power in a high performance microprocessor
Proceedings of the 19th international symposium on Physical design
A revisit to voltage partitioning problem
Proceedings of the 20th symposium on Great lakes symposium on VLSI
The fast optimal voltage partitioning algorithm for peak power density minimization
Proceedings of the International Conference on Computer-Aided Design
Fast approximation for peak power driven voltage partitioning in almost linear time
Proceedings of the International Conference on Computer-Aided Design
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With advancing technology, large dynamic power consumption has significantly limited circuit miniaturization. Minimizing peak power consumption, which is defined as the maximum power consumption among all voltage partitions, is important since it enables energy saving from the voltage island shutdown mechanism. In this paper, we prove that the peak power driven voltage partitioning problem is NP-complete and propose an efficient provably good fully polynomial time approximation scheme for it. The new algorithm can approximate the optimal peak power driven voltage partitioning solution in O(m2(mn/ε4)m) time within a factor of (1 + ε) for sufficiently small positive ε, where n is the number of circuit blocks and m is the number of partitions which is a small constant in practice. Our experimental results demonstrate that the dynamic programming cannot finish for even 20 blocks while our new approximation algorithm runs fast. In particular, varying ε, orders of magnitude speedup can be obtained with only 0.6% power increase. The tradeoff between the peak power minimization and the total power minimization is also investigated. We demonstrate that the total power minimization algorithm obtains good results in total power but with quite large peak power, while our peak power optimization algorithm can achieve on average 26.5% reduction in peak power with only 0.46% increase in total power. Moreover, our peak power driven voltage partitioning algorithm is integrated into a simulated annealing based floorplanning technique. Experimental results demonstrate that compared to total power driven floorplanning, the peak power driven floorplanning can significantly reduce peak power with only little impact in total power, HPWL, estimated power ground routing cost, level shifter cost and runtime. Further, when the voltage island shutdown is performed, peak power driven voltage partitioning can lead to over 10% more energy saving than a greedy frequency based voltage partitioning when multiple idle block sequences are considered.