Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
A provably good approximation algorithm for power optimization using multiple supply voltages
Proceedings of the 44th annual Design Automation Conference
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The approximation scheme for peak power driven voltage partitioning
Proceedings of the International Conference on Computer-Aided Design
Fast approximation for peak power driven voltage partitioning in almost linear time
Proceedings of the International Conference on Computer-Aided Design
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Increasing transistor density in nanometer integrated circuits has resulted in large on-chip power density. As a high-level power optimization technique, voltage partitioning is effective in mitigating power density. Previous works on voltage partitioning attempt to address it through minimizing total power consumption over all voltage partitions. Since power density significantly impacts thermal-induced reliability, it is also desired to directly mitigate peak power density during voltage partitioning. Unfortunately, none of the existing works consider this. This paper proposes an efficient optimal voltage partitioning algorithm for peak power density minimization. Based on novel algorithmic techniques such as implicit power density binary search, the algorithm runs in O(n log n + m2 log2 n) time, where n refers to the number of functional units and m refers to the number of partitions/voltage levels. Our experimental results on large testcases demonstrate that large amount of (about 9.7x) reduction in peak power density can be achieved compared to a natural greedy algorithm, while the algorithm still runs very fast. It needs only 14.15 seconds to optimize 1M functional units.