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In this paper, a rectilinear-based congestion-driven floorplanning algorithm is presented to enhance the wire congestion and the CPU runtime. The proposed algorithm contains two stages, including the simulated-annealing (SA) based approach with the concept of ant algorithm (SANTA) and the nonlinear programming based method. The objective of the first stage and the second stage are to minimize the multiple objectives, such as the area, wire length and wire congestion, and to further improve the wire congestion of the local congested region without the area overhead, respectively. First, the effective concept of the ant algorithm is integrated into the multiple objectives floorplanner, which simultaneously minimizes area, wire congestion and the total wire length, to speedup the runtime. Besides, the nonlinear programming (NLP) based formulations are provided to perform the module reshaping, which maximizes the common length between two adjacent congested modules. For the floorplanner, the sequential-pair (SP) presentation is utilized to deal with the floorplan data at every iteration. For each iteration of the floorplanner, we first use SANTA to improve the neighbor searching and reduce the runtime. After performing the first state, we will obtain a floorplan with the objectives of the area, wire congestion and total length. For the intermediate floorplan, we select the two adjacent soft modules located at the most congested regions and divide the two soft modules into a set of connected sub-rectangles. Hence, we further reduce the congestion by enlarging the common boundary between the selected adjacent modules. Of course, the modular reshaping technique significantly increases the common length and the capacity of pins to reduce the wire congestion by utilizing the nonlinear programming based approach. To deserve to be mentioned that there is no area overhead after we perform the modular reshaping for the selected adjacent modules. Compared to the results of the traditional SA, SANTA achieves an average improvement on the area, the total wire length and CPU runtime by 3% and 8.1% and 23.0%, respectively. To show the superior to our approach, 30 floorplan samples are randomly selected from Microelectronics Center of North Carolina (MCNC) benchmarks. The experimental result shows that the reshaping method improves the wire congestion and total wire length by 22% and 1.54%, respectively.