Parallel program design: a foundation
Parallel program design: a foundation
On the parallel implementation of Goldberg's maximum flow algorithm
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Parallel programming with MPI
An efficient implementation of a scaling minimum-cost flow algorithm
Journal of Algorithms
Verifying properties of parallel programs: an axiomatic approach
Communications of the ACM
Guarded commands, nondeterminacy and formal derivation of programs
Communications of the ACM
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proving the Correctness of Multiprocess Programs
IEEE Transactions on Software Engineering
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parallel programming: can we PLEASE get it right this time?
Proceedings of the 45th annual Design Automation Conference
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
An efficient incremental algorithm for min-area retiming
Proceedings of the 45th annual Design Automation Conference
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
MAPS: multi-algorithm parallel circuit simulation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
The Art of Multiprocessor Programming
The Art of Multiprocessor Programming
The multicore revolution: the challenges for theory
FSTTCS'07 Proceedings of the 27th international conference on Foundations of software technology and theoretical computer science
Minimizing wire length in floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation
Proceedings of the 47th Design Automation Conference
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel cross-layer optimization of high-level synthesis and physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and many-core microprocessors have the potential to offer scalable performance improvement. How to explore the multicore resources to speed up CAD applications is thus a natural question but also a huge challenge for CAD researchers. Indeed, decades of work on general-purpose compilation approaches that automatically extracts parallelism from a sequential program has shown limited success. Past work has shown that programming model and algorithm design methods have a great influence on usable parallelism. In this paper, we propose a methodology to explore concurrency via nondeterministic transactional algorithm design, and to program them on multicore processors for CAD applications. We apply the proposed methodology to the min-cost flow problem which has been identified as the key problem in many design optimizations, from wire-length optimization in detailed placement to timing-constrained voltage assignment. A concurrent algorithm and its implementation on multicore processors for min-cost flow have been developed based on the methodology. Experiments on voltage island generation in floorplanning demonstrated its efficiency and scalable speedup over different number of cores.