Relaxation techniques for the simulation of VLSI circuits
Relaxation techniques for the simulation of VLSI circuits
Accelerated waveform methods for parallel transient simulation of semiconductor devices
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An Asynchronous Parallel Supernodal Algorithm for Sparse Gaussian Elimination
SIAM Journal on Matrix Analysis and Applications
Parallel Transient Analysis for Circuit Simulation
HICSS '96 Proceedings of the 29th Hawaii International Conference on System Sciences Volume 1: Software Technology and Architecture
MAPS: multi-algorithm parallel circuit simulation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Parallel transistor level circuit simulation using domain decomposition methods
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Parallelizable stable explicit numerical integration for efficient circuit simulation
Proceedings of the 46th Annual Design Automation Conference
Multicore parallel min-cost flow algorithm for CAD applications
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Final-value ODEs: stable numerical integration and its application to parallel circuit analysis
Proceedings of the 2009 International Conference on Computer-Aided Design
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation
Proceedings of the 47th Design Automation Conference
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
What is parallel circuit simulation?
ACM SIGDA Newsletter
What is parallel circuit simulation?
ACM SIGDA Newsletter
Parallel transistor level full-chip circuit simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel circuit simulation with adaptively controlled projective integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Expression-Level Parallelism for Distributed Spice Circuit Simulation
DS-RT '11 Proceedings of the 2011 IEEE/ACM 15th International Symposium on Distributed Simulation and Real Time Applications
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation
Proceedings of the International Conference on Computer-Aided Design
Rapid Synthesis and Simulation of Computational Circuits in an MPPA
Journal of Signal Processing Systems
Time-domain segmentation based massively parallel simulation for ADCs
Proceedings of the 50th Annual Design Automation Conference
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While the emergence of multi-core shared-memory machines offers a promising computing solution to ever complex chip design problems, new parallel CAD methodologies must be developed to gain the full benefit of these increasingly parallel computing systems. We present a parallel transient simulation methodology and its multi-threaded implementation for general analog and digital ICs. Our new approach, Waveform Pipelining (abbreviated as WavePipe), exploits coarsegrained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step by moving backwards in time, the latter performs predictive computing along the forward direction of the time axis. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardying convergence and accuracy. As a coarse-grained parallel approach, WavePipe not only requires low parallel programming effort, more importantly, it creates new avenues to fully utilize increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions.