Relaxation techniques for the simulation of VLSI circuits
Relaxation techniques for the simulation of VLSI circuits
PARASPICE: a parallel circuit simulator for shared-memory multiprocessors
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
TETA: transistor-level engine for timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Mask verification on the connection machine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Iterative solution of nonlinear equations in several variables
Iterative solution of nonlinear equations in several variables
An Alternative Implementation of Variable Step-Size Multistep Formulas for Stiff ODEs
ACM Transactions on Mathematical Software (TOMS)
Numerical Initial Value Problems in Ordinary Differential Equations
Numerical Initial Value Problems in Ordinary Differential Equations
A Linear-Centric Modeling Approach to Harmonic Balance Analysis
Proceedings of the conference on Design, automation and test in Europe
Performance Evaluation of MPI Implementations and MPI-Based Parallel ELLPACK Solvers
MPIDC '96 Proceedings of the Second MPI Developers Conference
Performance Evaluation of a Parallel Iterative Method Library using OpenMP
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Parallelizable stable explicit numerical integration for efficient circuit simulation
Proceedings of the 46th Annual Design Automation Conference
Multicore parallel min-cost flow algorithm for CAD applications
Proceedings of the 46th Annual Design Automation Conference
Final-value ODEs: stable numerical integration and its application to parallel circuit analysis
Proceedings of the 2009 International Conference on Computer-Aided Design
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation
Proceedings of the 47th Design Automation Conference
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
What is parallel circuit simulation?
ACM SIGDA Newsletter
What is parallel circuit simulation?
ACM SIGDA Newsletter
Parallel transistor level full-chip circuit simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel circuit simulation with adaptively controlled projective integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation
Proceedings of the International Conference on Computer-Aided Design
Circuit simulation via matrix exponential method for stiffness handling and parallel processing
Proceedings of the International Conference on Computer-Aided Design
Time-domain segmentation based massively parallel simulation for ADCs
Proceedings of the 50th Annual Design Automation Conference
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The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing parallel computing power holds new promise to address many computing challenges in CAD, the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applications. In this paper, we propose a novel Multi-Algorithm Parallel circuit Simulation approach (MAPS) and its multi-core implementation to expedite one of the most fundamental CAD applications: transistor-level transient circuit simulation. MAPS starts multiple simulation algorithms in parallel for a given simulation task. By properly synchronizing these algorithms on-the-fly, we exploit the diversity in simulation algorithms to achieve possibly superlinear overall speedup in transient simulation. In addition, our unique multi-algorithm framework allows unique safe exploration of simulation methods that are conventionally discarded due to convergence concerns. As a coarse grained parallel simulation approach, the implementation of MAPS demands a minimum of parallel programming effort and allows for reuse of existing serial simulation codes.