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Transistor-level circuit simulation, i.e. SPICE simulation [1], is a fundamental tool for design and verification of a wide range of integrated circuits such as memories, custom digital ICs, analog, mixed-signal and RF circuits as well as digital cell library characterization. It is common for today's designers to spend days, weeks or even months of CPU time to perform expensive transistor-level circuit analysis. The simulation bottleneck significantly limits pre-silicon verification and design space exploration, contributing to long design turnaround time, suboptimal designs and even chip failures. With the advent of more complex device models and increased design complexity, high-capacity circuit simulation is strongly desirable in order to boost design productivity.