TETA: transistor-level engine for timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
An Asynchronous Parallel Supernodal Algorithm for Sparse Gaussian Elimination
SIAM Journal on Matrix Analysis and Applications
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
MAPS: multi-algorithm parallel circuit simulation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multicore parallel min-cost flow algorithm for CAD applications
Proceedings of the 46th Annual Design Automation Conference
GPU-based parallelization for fast circuit optimization
Proceedings of the 46th Annual Design Automation Conference
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation
Proceedings of the 47th Design Automation Conference
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The past several years have witnessed a significant interest in developing parallel CAD algorithms and implementations that exploit various multi-core and distributed computing hardware. In addition to fundamental parallel algorithm design, the ability in modeling parallel performance and facilitating runtime optimization is indispensable for achieving good efficiency for complex parallel CAD applications. Under the context of a recently developed hierarchical multi-algorithm parallel circuit simulation (HMAPS) framework, we demonstrate a runtime optimization approach that allows for automatic on-the-fly reconfiguration of the parallel simulation code. We show how the runtime information, collected as parallel simulation proceeds, can be combined with static parallel performance models to enable dynamic adaptation of parallel simulation execution for improved performance and robustness. Our results have shown that the proposed approach not only finds the near-optimal code configuration over a large configuration space, it also outperforms multi-algorithm circuit simulation assisted only with static pre-runtime parallel performance modeling.