A backplane approach for cosimulation in high-level system specification environments
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Comparing models of computation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Heterogeneous and Distributed Co-Simulation Environment
Proceedings of the 15th symposium on Integrated circuits and systems design
A Parallel and Accelerated Circuit Simulator with Precise Accuracy
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the 35th conference on Winter simulation: driving innovation
Formal Definitions of Simulation Interfaces in a Continuous/Discrete Co-Simulation Tool
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
Proceedings of the 45th annual Design Automation Conference
Parallel transistor level circuit simulation using domain decomposition methods
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast circuit simulation on graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
OpenMP implementation of SPICE3 circuit simulator
International Journal of Parallel Programming
Accelerating SPICE Model-Evaluation using FPGAs
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Dynamic resolution in distributed cyber-physical system simulation
Proceedings of the 2013 ACM SIGSIM conference on Principles of advanced discrete simulation
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Distributed system-level simulation among coordinated, heterogeneous simulators requires communication and synchrony to preserve event causality. Once achieved, multiple coordinated, distributed instances of a single simulator not originally written for internal parallelism can be used to conduct the expression-level parallel execution of a model partitioned into subsystems, such that each subsystem is assigned to an individual simulator. Using a Kahn Process Network simulation back plane for coordination, and a custom Xspice TCP/IP socket device for interfacing, expression-level distributed simulation was applied to observe a decrease of up to 1/52 times the transient analysis time of the same circuit in a single Ngspice instance, without modifying the Ngspice kernel or host execution environment. Up to 128 independent Ngspice instances were coordinated in parallel with this method, with a selectable tradeoff in speed versus accuracy.