Expression-Level Parallelism for Distributed Spice Circuit Simulation
DS-RT '11 Proceedings of the 2011 IEEE/ACM 15th International Symposium on Distributed Simulation and Real Time Applications
| Hi-index | 0.00 |
Abstract: This paper presents a new framework and its prototype implementation for the distributed simulation of a mixed-signal system where some parts are modeled by differential and algebraic equations (as in SPICE) and other parts are modeled by discrete events (as in VHDL or Verilog). The work is built on top of a general-purpose framework of parallel and distributed simulation that combines both conservative and optimistic synchronization methods to extract the maximum concurrency available in such mixed analog and digital systems. We demonstrate that, the maximum speedup can be achieved with digital components using optimistic scheduling and analog components using conservative scheduling. A technique to further increase the parallelism among simultaneous events without sacrificing the simulation accuracy is proposed, by using a coarser time grain for the internal step events of analog solvers. Experimental results demonstrate a 6.2X speed-up on 8 processors for a circuit described in VHDL and SPICE. This paper details our implementation, including how to make the numerical integration used by analog electrical-level simulation event-driven and to synchronize it with digital behavioral and gate-level simulation, analog and digital conversions, and how to resolve the non-convergence arising from straightforward analog and digital simulator integration. This paper also shows, for the first time, that optimistic synchronization for distributed analog simulation is feasible and quite efficient for small-to-medium size analog blocks.