High-Performance Electrical Signaling
MPPOI '98 Proceedings of the The Fifth International Conference on Massively Parallel Processing Using Optical Interconnections
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication latency aware low power NoC synthesis
Proceedings of the 43rd annual Design Automation Conference
Energy and switch area optimizations for FPGA global routing architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High performance on-chip differential signaling using passive compensation for global communication
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
What is the design challenge for on-chip speed-of-light communication?
ACM SIGDA Newsletter
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We present a novel scheme to implement distortion- less transmission lines for on-chap edectracal signaling. By introducing intentional leakage conductance between the wires of a differential pair, the distortionless trans- mission line eliminates dispersion caused b y the resis- tive nature of on-ch ip wires and achieves speed of light transmission. We show that it is feasible to construct distortionless transmission line with conventional sili- con process. Simulation results show that using 65nm technology, the proposed scheme can achieve 15Gbits/s bandwidth over a 20mm on-chip serial link without any equalization. This approach offers a six times improve- ment in delay and 85% reduction in power consumption over a conventional RC wire with repeated buffers.