A 9-Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines

Authors:
JunYoung Park;Joshua Kang;Sunghyun Park;Michael P. Flynn
Affiliations:
Qualcomm, San Diego, CA and University of Michigan, Ann Arbor, MI;Marvell Semiconductor, Inc., Santa Clara, CA and University of Michigan, Ann Arbor, MI;Qualcomm, San Diego, CA and University of Michigan, Ann Arbor, MI;Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Year:
2009

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Abstract

A 9-Gbit/s serial link transceiver for on-chip global signaling, and techniques for the design of on-chip transmission lines, are presented. In a prototype device, a transmitter serializes 8-b 1.125-Gbyte/s parallel data and transmits serial data over a 5.8-mm lossy on-chip transmission line. A receiver deserializes the received data with the help of a digitally tuned interpolator. An on-chip lossy transmission line scheme is described. In the prototype, self-test circuitry verifies the recovered, deserialized data against the original data and counts the number of discrepancies. The prototype transceiver, implemented in 0.13-µm 8-metal CMOS, achieves 9 Gbit/s with pre-defined data patterns.