Layout compaction for yield optimization via critical area minimization
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Area routing oriented hierarchical corner stitching with partial bin
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Fast Multi-Layer Critical Area Computation
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
DFM: Linking Design and Manufacturing
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Problem-Solving Methods in Artificial Intelligence
Problem-Solving Methods in Artificial Intelligence
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Maze routing with buffer insertion and wiresizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.