Post-routing redundant via insertion and line end extension with via density consideration
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Conjugate conflict continuation graphs for multi-layer constrained via minimization
Information Sciences: an International Journal
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A yield-driven gridless router
Journal of Computer Science and Technology
Simultaneous redundant via insertion and line end extension for yield optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Until the move to the 130nm node, yield was an issue only for product engineers and engineers on the production line. Design engineers did not need to think explicitly about yield, or understand the manufacturing process. Beginning at the 130nm node, yield has become more problematic, and the defect mechanisms that contribute to yield loss are very different. Where random defects used to be dominant, we now have defects due to lithographic issues, and pattern (or design) dependent issues. This tutorial will explain how these latter defect mechanisms differ from random defects and how and why the design engineer needs to become involved to mitigate the problem. On the lithography topic, this tutorial will briefly examine techniques such as OPC (Optical Proximity Correction) and PSM (Phase Shift Masking), and explain their design and yield impact. We will also examine issues such as dummy metal fill for CMP, redundant via insertion, as ways to mitigate pattern dependent yield issues.