The R*-tree: an efficient and robust access method for points and rectangles
SIGMOD '90 Proceedings of the 1990 ACM SIGMOD international conference on Management of data
Introduction to Algorithms
R-trees: a dynamic index structure for spatial searching
SIGMOD '84 Proceedings of the 1984 ACM SIGMOD international conference on Management of data
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Guest Editors' Introduction: Design for Yield and Reliability
IEEE Design & Test
Physical CAD changes to incorporate design for lithography and manufacturability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DFM: Linking Design and Manufacturing
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Embedded tutorial I: design for manufacturability
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Redundant via insertion with wire bending
Proceedings of the 2009 international symposium on Physical design
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
Proceedings of the 2009 International Conference on Computer-Aided Design
Enhanced double via insertion using wire bending
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous redundant via insertion and line end extension for yield optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
Microelectronics Journal
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Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. However, if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design. In this paper, we first study the problem of redundant via insertion, and present two methods to accelerate a state-of-the-art approach (which is based on a maximum independent set (MIS) formulation) to solve it. We then consider the problem of simultaneous redundant via insertion and line end extension. We formulate the problem as a maximum weighted independent set (MWIS) problem and modify the accelerated MIS-based approach to solve it. Lastly, we investigate the problem of simultaneous redundant via insertion and line end extension subject to the maximum via density rule, and present a two-stage approach for it. In the first stage, we ignore the maximum via density rule, and enhance the MWIS-based approach to find the set of regions which violate the maximum via density rule after performing simultaneous redundant via insertion and line end extension. In the second stage, excess redundant vias are removed from those violating regions such that after the removal, the maximum via density rule is met while the total amount of redundant vias removed is minimized. This density-aware redundant via removal problem is formulated as a set of zero-one integer linear programming (0-1 ILP) problems each of which can be solved independently without sacrificing the optimality. The superiorities of our approaches are all demonstrated through promising experimental results.