Guest Editors' Introduction: Design for Yield and Reliability
IEEE Design & Test
Physical CAD changes to incorporate design for lithography and manufacturability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DFM: Linking Design and Manufacturing
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Practical aspects of reliability analysis for IC designs
Proceedings of the 43rd annual Design Automation Conference
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Post-routing redundant via insertion and line end extension with via density consideration
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Redundant Via Insertion in Restricted Topology Layouts
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
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As VLSI design complexity is continuously increasing, the yield loss due to via failure becomes more significant. Adding a redundant via adjacent to each single via is a well-known and highly recommended method to reduce yield loss due to via failure. In this paper, we develop a network-flow-based algorithm in post-layout stage for the redundant via insertion problem. With our novel and efficient approach, we can obtain optimal redundant via insertion solution in improving the manufacturing yield, with minimal fixup if necessary. Moreover, our approach is parallel-processing-friendly and effective in ECO incremental solution due to the nature of network-flow models.