Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
A Simple via Duplication Tool for Yield Enhancement
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Post-routing redundant via insertion and line end extension with via density consideration
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Double-via-driven standard cell library design
Proceedings of the conference on Design, automation and test in Europe
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion with wire spreading capability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Redundant via insertion with wire bending
Proceedings of the 2009 international symposium on Physical design
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Routing for manufacturability and reliability
IEEE Circuits and Systems Magazine
Enhanced double via insertion using wire bending
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal double via insertion with on-track preference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an improved multilevel Full-chip routing system which integrates global routing and detailed routing algorithms to achieve great enhancement in yield and reliability considering the redundant via placement. The system features a pre-coarsening stage which is equipped with a fast congestion-driven L-pattern global routing followed by the rvia-driven detailed routing. The L-pattern global routing benefits a lot to the reduction of vias and thus relieves the burden of redundant via addition. Then the rvia-driven maze routing algorithm considers the addition of redundant vias during routing. Finally the redundant via placement heuristic also contributes to improve the completion rate. We have tested the system on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing framework. The experimental results are promising.