Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Simultaneous redundant via insertion and line end extension for yield optimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited capability of placing more double vias (called vial) between metal 1 and metal 2. Such a limitation is caused by the way we design the standard cells and can not be resolved by developing better tools. This paper presents a double-via-driven standard cell library design approach to solving this problem. Compared to the results obtained using a commercial cell library, our library on average achieves 78% reduction in dead vias and 95% reduction in dead vials at the expense of 11% increase in total via count. We achieve these results (almost) at no extra cost in total cell area and wire length.