Optimal double via insertion with on-track preference

Authors:
Kuang-Yao Lee;Ting-Chi Wang;Cheng-Kok Koh;Kai-Yuan Chao
Affiliations:
Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;Intel Corporation, Hillsboro, OR
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

Citing 5
Cited 0

A Simple via Duplication Tool for Yield Enhancement

DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Improved multilevel routing with redundant via placement for yield and reliability

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Post-routing redundant via insertion for yield/reliability improvement

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Full-Chip Routing Considering Double-Via Insertion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and Optimal Redundant Via Insertion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.04

Visualization

Abstract

As on-track double vias take less routing resources and have better electrical characteristics, we study in this paper the problem of double via insertion with a preference for on-track double vias (DVI/ON) in a postrouting stage. The primary goal is to insert as many double vias as possible, and maximizing the number of on-track double vias is a secondary objective. We present a zero-one integer linear program-based approach to optimally solve the DVI/ON problem. Moreover, we also discuss a special case of the DVI/ON problem and present a maximum-weighted bipartite matching-based optimal approach. Experimental results indicate that our approaches outperform existing algorithms in terms of solution quality.