Optimal layer assignment for interconnect
Advances in VLSI and Computer Systems
Layer Assignment Problem for Three-Layer Routing
IEEE Transactions on Computers
The Via Minimization Problem is NP-Complete
IEEE Transactions on Computers
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Integration, the VLSI Journal
Fast algorithm for optimal layer assignment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A graph-partitioning-based approach for multi-layer constrained via minimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering for VLSI Applications
IEEE Transactions on Computers
Three-quarter approximation for the number of unused colors in graph coloring
Information Sciences: an International Journal
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Layer assignment for crosstalk risk minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DFM: Linking Design and Manufacturing
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An adaptive genetic algorithm for the minimal switching graph problem
EvoCOP'05 Proceedings of the 5th European conference on Evolutionary Computation in Combinatorial Optimization
An efficient approach to multilayer layer assignment with an application to via minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A layout modification approach to via minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum-Via Topological Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Antenna avoidance in layer assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Max-k-Cut by the Discrete Dynamic Convexized Method
INFORMS Journal on Computing
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A graph model for describing the relationships among wire segments is crucial to constrained via minimization (CVM) in a VLSI design. In this paper we present a new graph model, called the conjugate conflict continuation graph, for multi-layer CVM with stacked vias. This graph model eases the handling of stacked via problems. An integer linear programming (ILP) formulation and a simulated annealing (SA) algorithm based on this graph model are developed to solve multi-layer CVM. The ILP model is too complicated to solve efficiently. The SA algorithm on average achieves 6.4% via reduction for layouts obtained using a commercial tool under a set of practical constraints in which the metal wires (including pins) used in cell layouts, power rails and rings, and clock routing are treated as obstacles or fixed-layer objects to a multi-layer CVM.