Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
Simultaneous driver and wire sizing for performance and power optimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Memory-efficient interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On mismatches between incremental optimizers and instance perturbations in physical design tools
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With the increasing influence of the resistive effects of interconnects on the performance of VLSI systems, a great stress is being laid on careful interconnect design. One prominent technique is the approach of sizing long interconnects to achieve the desired speed and power characteristics. It has also been suggested that one may appropriately insert repeaters for significant delay reductions. This paper unifies these approaches to optimizing an interconnect by placing a prespecified number of buffers (drivers and repeaters) using a dynamic programming procedure and then performing simultaneous wire and buffer sizing using a sensitivity-based heuristic. Experimental results are presented to prove the utility and performance of the approach.