Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Journal of Signal Processing Systems
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
Proceedings of the 2008 international symposium on Physical design
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Ultra-fast interconnect driven cell cloning for minimizing critical path delay
Proceedings of the 19th international symposium on Physical design
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
SPIRE: a retiming-based physical-synthesis transformation system
Proceedings of the International Conference on Computer-Aided Design
CATALYST: planning layer directives for effective design closure
Proceedings of the Conference on Design, Automation and Test in Europe
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Closed-form expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently have large blocks that make the ideal buffer-insertion solution unrealizable. The theory of Otten (ACM/IEEE Intl. Symp. Physical Design, p. 104, 1998) is extended to show how one can model the blocks into a simple delay-estimation technique that applies to both two-pin and multipin nets. Even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer-insertion solution. Potential applications include wire planning, timing analysis during floorplanning, or global routing. The authors' experiments show that their approach accurately predicts delay when compared to constructing a realizable buffer insertion with multiple buffer types