RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm

Authors:
David A. Papa;Tao Luo;Michael D. Moffitt;C. N. Sze;Zhuo Li;Gi-Joon Nam;Charles J. Alpert;Igor L. Markov
Affiliations:
University of Michigan, Ann Arbor, MI, USA and IBM Austin Research Lab, Austin, TX;University of Texas at Austin, Austin, TX, USA;IBM Austin Research Lab, Austin, TX, USA;IBM Austin Research Lab, Austin, TX, USA;IBM Austin Research Lab, Austin, TX, USA;IBM Austin Research Lab, Austin, TX, USA;IBM Austin Research Lab, Austin, TX, USA;University of Michigan, Ann Arbor, MI, USA
Venue:
Proceedings of the 2008 international symposium on Physical design
Year:
2008

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Abstract

Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical to success. We present a new physical synthesis optimization for latch placement called RUMBLE (Rip Up and Move Boxes with Linear Evaluation) that uses a linear timing model to optimize timing by simultaneously re-placing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. Experimental results validate the effectiveness of the approach: our techniques improve slack by 41.3% of cycle time on average for a large commercial ASIC design