DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A fast algorithm for context-aware buffer insertion
Proceedings of the 37th Annual Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The scaling of interconnect buffer needs
Proceedings of the 2006 international workshop on System-level interconnect prediction
Maze routing steiner trees with effective critical sink optimization
Proceedings of the 2007 international symposium on Physical design
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
Proceedings of the 2008 international symposium on Physical design
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
Proceedings of the International Conference on Computer-Aided Design
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Buffer insertion is an increasingly critical optimization for achieving timing closure, and the number of buffers required increases significantly with technology migration. It is imperative for an automated buffer insertion algorithm to be able to efficiently optimize tens of thousands of nets. One must also be able to effectively navigate the existing layout, including handling large blockages, blockages with holes specifically for buffers, specially allocated buffer blocks, placement porosity, and routing congestion. The algorithm must also be flexible enough to know when to use and when not to use expensive layout resources. Although several previous works have addressed buffer insertion in the presence of blockages, this is the first to present a complete solution that can manage the physical layout environment.