Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Fast and flexible buffer trees that navigate the physical layout environment
Proceedings of the 41st annual Design Automation Conference
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A practical methodology for early buffer and wire resource allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On controlling perturbation due to repeaters during quadratic placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Since wires scale worse than devices, their quadratic delay is often linearized through buffer insertion, leading to a rapid increase in the number of buffers in a design when it is shrunk to successive process nodes. This increase was quantified in an influential work in 2003 by scaling the wiring distribution of a design block and measuring the number of buffers required by it at different process nodes. In this paper, we study the robustness of the data points presented in that work by examining their underlying assumptions. Finally, we revisit the CAD and design implications of buffer count growth, in light of current design trends.